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Si4355
6. Data Handling and Packet Handler
6.1. RX FIFO
A 64-byte RX FIFO is integrated into the chip. Reading from command register 77h reads data from this RX FIFO.
6.2. Packet Handler
The Si4355 includes integrated packet handler features such as preamble and sync word detection as well as CRC
calculation. This allows the chip to qualify and synchronize with legitimate transmissions independent of the
microcontroller. These features can be enabled using the EZConfig setup. In this setup, the preamble and sync
word length can be modified and the sync word pattern can be selected. The general packet structure is shown in
Figure 12.
There is also the option within the EZConfig setup to select a variable packet length. With this setting, the receiver
is not required to know the packet length ahead of time. The transmitter sends the length of the packet immediately
after the sync word. The packet structure for variable length packets is shown in Figure 13.
Preamble
0 – 255 Bytes
Sync Word
1 – 4 Bytes
Data
1 – 64 Bytes
CRC
2 Bytes
Figure 12. Packet Structure for Fixed Packet Length
Preamble
0 – 255 Bytes
Sync Word
1 – 4 Bytes
Length
1 Byte
Data
1 – 64 Bytes
CRC
2 Bytes
Figure 13. Packet Structure for Variable Packet Length
26
Rev 1.0
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